1. Field of Invention
The invention concerns a process for the production of high-speed vertical npn-bipolar transistors and complementary MOS-transistors on a chip.
2. Description of Related Art
BiCMOS-technologies are used for the production of integrated circuits or circuit blocks which include both MOS-transistors with a p- and an n-channel and also bipolar transistors. Modern BiCMOS-technologies aim specifically at combining circuit blocks with very high-speed bipolar transistors and very highly integrated CMOS logic on a chip in order to achieve powerful technological platforms for wireless and optical waveguide-based telecommunications. In consideration of the immense expenditure in terms of development and qualification of a very highly integrated CMOS technology, the modular integration of bipolar transistors into a qualified CMOS-technology is the most economical way of implementing such a modern BiCMOS-technology. Modular integration denotes in that respect that the influence of the additional process steps which are required for manufacture of the bipolar transistors on the parameters and yield of the CMOS transistors is kept so low that the circuitry libraries of the CMOS-technology can also be used for the BiCMOS-technology which is derived therefrom.
The best high-frequency characteristics of Si-based bipolar transistors are achieved at the present time with SiGe-hetero-bipolar transistors (SiGe-HBT). For that reason SiGe-HBT are also used for high-power BiCMOS-technologies, as described for example in G. Freeman: ‘A 0.18 μm 90 GHz fT SiGe HBT BiCMOS, ASIC-Compatible, Copper Interconnect Technology for RF and Microwave Applications’ Technical Digest of the 1999 International Electron Devices Meeting, pages 569–572 and R. Tang et al.: ‘A Low-Cost Modular SiGe BiCMOS Technology and Analog Passives for High-Performance RF and Wide-Band Applications’ Proceedings of the 2000 Bipolar/BiCMOS Circuits and Technology Meeting, pages 102–105. It is characteristic in respect of those technologies that essential process steps for integration of the HBTs into the original CMOS-process and for production of the HBTs themselves, such as the deposit of various protective layers, the SiGe-base layer and the emitter layer, are effected after production of the CMOS-wells, gate oxidation, gate structuring and (in the first publication quoted) doping and restoration of the MOS-transistors with an n-channel. That specific procedure for the production of bipolar transistors within a BiCMOS-technology has the disadvantage that it is not possible to completely exclude influencing of the vertical and lateral doping profiles of the CMOS-transistors by HBT-process steps, in particular by virtue of the given thermal budget thereof. The consequence of this can be that the original CMOS-transistor parameters cannot be exactly reproduced in the BiCMOS-process.
Theoretically that disadvantage can be avoided if all technological process steps which are employed for integration and production of the bipolar transistors were effected prior to the production of the wells and the gate insulating layer for the MOS-transistors. It will be noted that with that operating procedure the CMOS-process steps then act on the bipolar structures, which causes extreme difficulty in implementation of the steep doping profiles necessary for very good high-frequency properties, in particular in the base of the bipolar transistors. That applies in particular in regard to SiGe-HBTs, where a widening of the base doping profile (boron) beyond the edges of the SiGe-layer results in the formation of parasitic conduction band barriers which make it impossible to achieve very good high-frequency properties. CMOS-process steps which are particularly critical in terms of their effect on the doping profiles of bipolar transistors are gate oxidation and, when employed, reoxidation of the polysilicon gates, both just by virtue of the thermal budget which is usually involved in that respect. When those steps have an effect on unprotected single-crystal regions of the bipolar structures, the so-called OED effect is additionally involved (OED—Oxidation Enhanced Diffusion). A further critical CMOS-process step is restoration of the implant which is used for doping of the gate and source-drain regions of the MOS-transistors with an n-channel.